In general, wafer-scale integrated circuitry has been fabricated in a manner such that electronic elements or circuits are fabricated on a wafer and testing is provided by using external means, such as external testing circuits using suitable probes to connect to the wafer-scale elements or circuits to be tested. Such external testing means are used to determine which elements, or which circuits, or parts thereof, on a wafer are operable and which are not. Such technique is specially devised so as to address specific elements or circuits at different regions of the wafer using what is generally referred to as test vectors. As the complexity and density of circuits and elements on a wafer increase, the effectiveness of such a vector testing approach decreases, especially for regions which are imbedded relatively deeply within the wafer. Moreover, as complexity of the circuitry and elements placed on a wafer increases, a point is reached where the likelihood of being able to manufacture a wafer with all of its elements working correctly is extremely low so that the manufacturing process has a very low yield.
More recently, it has been proposed to use on-wafer redundancy techniques wherein redundant elements, or redundant circuits, or parts thereof, are placed on the wafer so as to improve both the testability and the yields thereof. Such redundancy was believed to be especially promising for use in creating relatively homogeneous and regular structures, such as memories, where additional rows and columns of bits can be placed on a wafer both to test its function and to replace faulty regions. It was proposed, for example, to replace defective rows and columns of bits with redundant counterparts on the same wafer, by using techniques, such as fusing appropriate intercomponent links using a laser.
However, it is found that using an active process, such as fusing links with a laser, can itself induce further defects in the elements or circuits of a wafer and requires still further testing and possible further reconfiguration after the initial reconfiguration phase of the production process has been completed. Moreover, the process is time consuming and must be customized for each wafer, so that it is extremely difficult to implement such technique on a mass production basis. The yields thereof are relatively low, while the cost is relatively high. Moreover, when using irregular circuits, such as processors or other randomly shaped or placed logic elements, it is very difficult to devise comprehensive on-wafer test circuits. The test circuits themselves tend to become so complex that their correct functioning may not be assured and they must also be checked. Since all circuits on a wafer are generally in close physical proximity to each other, they tend to share common mode failures, i.e., faults which affect several redundant components at the same time, which faults can defeat the use of redundant circuits or elements on the wafer. Such fault tolerant techniques for on-wafer redundancy, as well as for vector testing techniques, have generally been relatively unwieldly, complex and ineffective.